SIMPLIS JFET Options
The default test conditions for the Extract JFET Parameters dialog can be set from the menu Three advanced options are hidden by default until you click the Show Advanced Options button.
| Test Condition | Default Value | Units | Description |
| Collector to emitter voltage | 2k | V | The
peak off-state voltage seen by this device. Used to extract capacitance for model levels which include parasitic capacitance. Breakdown is not modeled. |
| Gate drive voltage | 15 | V | Gate to emitter voltage to extract RDS(on). |
| Collector current | 200 | A | Peak collector current to extract the RDS(on) and forward gain of the IGBT. |
| Model temperature | 25 | °C | Temperature used for all extraction simulations. |
| Model level | 0 | Model complexity. For information on choosing the model level, see IGBT Model Levels. | |
| Limit maximum off resistance | Checked | none | Limits the off resistance for the IGBT. For some SPICE models, this will produce a SIMPLIS model which runs faster. |
| Maximum off resistance | 100Meg | Ω | The maximum off resistance of the IGBT switch. This value is used only if "Limit maximum off resistance" is checked. |
| Option | Default Value | Description |
| Initial Place Preference | Extracted | Indicates which model type (Extracted or User-defined) is selected when you place the device on the schematic. |
| Automatically copy extracted parameters to User-defined parameters | Checked | If checked the extracted
parameters overwrite the user-defined parameters each time a model is
extracted. If unchecked, the user-defined parameters are never overwritten. |
| Debug | ||
| Output parameter ... | Unchecked | If checked, the debug statements
are automatically written to the deck file. The Command shell menu opens the .deck file for editing. An example set of debug statements can be found in the Deck-Level Debug section. |
| Advanced options | Hidden | Click this button to view or
change the advanced options. For more information, see Advanced Options. |
Deck-Level Debug
If you check "Output parameter debug statements to the deck file," each JFET in the design has a debug report inserted in the .deck file when you run a simulation. This debug report displays the calculated values for each major parameter in a formatted table. You can edit the .deck file with the Command shell menu . A sample debug report is shown below.
***SIMPLIS DEBUG EXTRACTED JFET START******************************************* *** *** *** Device with REF : Q2 *** *** *** *** Extracted from SPICE model: J108/PS *** *** *** ******************************************************************************** * * Model Extraction Parameters * * VD_PEAK : 25 * ID_PEAK : 25m * VGSOFF : -25 * TEMP : 25 * LEVEL : 0 * POL : 1 * LIMIT_MAX_ROFF : 1 * MAX_ROFF : 100Meg * * * Conduction Parameters * * RDSON : 14.5671 * ROFF : 999.796k * * Forward Gain Parameters * * VT0 : 5.15828 * HYSTWD : 515.828m * * Gate Resistance * * RG : 1.63278 * * Gate - Source Capacitance Parameters * * CGS : 4.1769p * * Drain - Gate Capacitance Parameters * * CDG : 6.46856p * * * Drain - Source Capacitance Parameters * * CDS_NSEG = 0, No CDS Capacitor is used * ******************************************************************************** *** *** *** Device with REF : Q2 *** *** *** *** Extracted from SPICE model: J108/PS *** *** *** ***SIMPLIS DEBUG EXTRACTED JFET END*********************************************