Rapid digital prototyping at the concept stage, thorough verification of the synthesizable digital design in the full analog application circuit before committing to silicon.
The new SIMPLIS Verilog-HDL Co-simulation module enables the fast, industry-verified SIMPLIS analog simulation engine to run in parallel with a Verilog-HDL simulation engine to permit users to analyze a behavioral or gate-level digital IC design operating in an actual analog application circuit instead of merely pairing it with an artificial input stimulus test bench. Designers interested in exploring new digital control algorithms can use behavioral Verilog-HDL syntax to get their ideas to the testing stage without having to delve into gate-level design. At verification time, the designer can test the performance of the synthesizable Verilog-HDL design against the original application circuit specifications before submitting it to silicon layout.
SIMPLIS VH is an add-on available to users of SIMetrix/SIMPLIS Pro and SIMetrix/SIMPLIS Elite. SIMPLIS VH cannot run properly without the SIMetrix Verilog-HDL capabilities present in those versions of the program.
At its core, SIMPLIS VH consists of the following elements:
SIMetrix/SIMPLIS Pro VH and SIMetrix/SIMPLIS Elite VH ship with the following versions of the open-source Icarus Verilog simulator:
SIMetrix/SIMPLIS Pro VH and SIMetrix/SIMPLIS Elite VH also support Siemens' ModelSim (former Mentor Graphics' ModelSim) versions 10.4 and later.
SIMPLIS VH expects its configuration file to be named "simplis_verilog.cfg" and to be located in the same directory as the SIMPLIS binary. The default Verilog-HDL simulator for SIMPLIS VH is the older stable version of Icarus, v0.9.1, and the configuration file that ships in the bin directory reflects that. Additional configuration files are available in the support/veriloghdl/config directory:
The Icarus configuration files should be all set and ready to use, just copy the appropriate one into the SIMPLIS bin directory and rename it to overwrite the default simplis_verilog.cfg file. The ModelSim configuration files will probably need customization depending on the installed version and the choice of installation directory. More information on setting up SIMPLIS VH to use ModelSim can be found in the section titled Configuring SIMPLIS VH to work with ModelSim.
The default simplis_verilog.cfg file is heavily commented, with information on each of the supported flags and fields, and this is the entirety of the configuration file syntax documentation. It should be noted here that changes to the .cfg file that improperly configure SIMPLIS VH and/or the selected Verilog-HDL simulator can lead to warnings, errors, crashes and hangs.
Once configured, a user interacts with SIMPLIS VH principally in the following ways:
So long as the Verilog-HDL code is supported by the SIMetrix Verilog-HDL symbol creation process, it should work for the SIMPLIS Verilog interface as well. First, make sure that you have saved your schematic.
The Verilog-HDL specification allows for a certain amount of parameterization of modules. Both the SIMetrix and SIMPLIS Verilog-HDL interfaces support the passing of parameters to a Verilog-HDL source module. Parameter names and default values are configured inside of the Verilog-HDL source file using the standard syntax. A simple example that would pass an initial condition value to a module might look something like the following:
parameter IC = 0;
During the symbol creation process, the parameter names and default values are extracted from the Verilog-HDL module definition and added to the list of parameters configurable through the standard Edit dialog (available by double-clicking the device or selecting it and hitting F7). Adding or removing parameters from the Verilog-HDL source file will require re-creating the symbol in order to be reflected in the Edit dialog.
To facilitate debugging during schematic and Verilog HDL development, we have added a custom VPI task ($simplis_vpi_probe) that will pass any changes in a wire (vpiNet) or register (vpiReg) through SIMPLIS to the SIMetrix/SIMPLIS waveform viewer. The task can also monitor changes in a vpiPartSelect that implements vpiConstantSelect; however not all simulators support that properly, so that support should not be counted on unless independently verified. Because the changes do not have to be written to a text log (as a $monitor or $display would require), there is often a performance advantage to using the built-in task as well. The syntax is fairly simple:
initial $simplis_vpi_probe( wire_or_register_name );
To see it in action, check out the PID Compensator used in the Digital PWM example. Open and run the following schematic from the examples directory:
SIMPLIS\Verilog-HDL\Digital_PWM_with_Verilog_HDL\Main Schematics\VH_SyncBuck_Digital_PWM.sxsch
Notice that the PID_out signal does not have an associated probe on the schematic. If you look at the text of the Verilog source file:
SIMPLIS\Verilog-HDL\Digital_PWM_with_Verilog_HDL\Verilog_Lib\PID_compensator.v
You will see the call to $simplis_vpi_probe in one of the initial blocks. It is recommended that calls to $simplis_vpi_probe not be placed inside always blocks as that could lead to a performance hit under certain circumstances with certain simulators. For the provided Icarus simulators, it will probably not be noticeable, however, in the future that may change.
Note that you will be responsible for handling any naming collisions. As with a normal SIMetrix/SIMPLIS probe, having two signals with the same name will lead to unpredictable results.
Also, data from calls to $simplis_vpi_probe will most often not be available until the simulation completes (as if "Plot on Completion" had been selected in the Edit Probe dialog for a regular voltage probe).
Finally, there is no conditional probing. Wrapping a call to $simplis_vpi_probe in an if statement will have no effect. If a call to $simplis_vpi_probe exists in the Verilog source, then that signal will be probed regardless of any programmatic logic that may or may not surround it in the .v file.
Starting with v8.40, SIMPLIS VH will place the following line at the top of the vss_root.v module, before the `include statements:
`define SIMPLIS_VH_INTERFACE_PRESENT 1
If desired, Verilog-HDL authors can use an `ifdef directive in conjunction with the macro to wrap any SIMPLIS VH-specific content.
Beginning with SIMetrix/SIMPLIS v9.00, SIMPLIS VH can now co-simulate with both 32-bit and 64-bit versions of Modelsim, one of which must be installed on the same PC as SIMPLIS VH. There is no longer a self-serve evaluation license generator for ModelSim, but a speed-limited free version is available from Intel's FPGA site. The download page and self-service licensing page should allow for running SIMPLIS VH with the "Questa - Intel FPGA Edition (Starter Edition)" package.
Once you have downloaded and installed ModelSim, and gotten it to run an example circuit (thus ensuring that the license is working as intended), the following changes should be made to the Windows environment in order to support simulations from the command line. Adjust the path to the ModelSim installation directory accordingly.
set PATH=%PATH%;C:\modeltech_pe_10.4\win32pe
set PATH=%PATH%;C:\intelFPGA_pro\21.3\questa_fse\win64
set LM_LICENSE_FILE=C:/modeltech_pe_10.4/win32pe/license.txt
set MODELSIM=C:\modeltech_pe_10.4\modelsim.ini
When the environment variables are set, you should be able to invoke vsim from the command line and it will check for a license (and launch the GUI if no arguments are provided).
Next, modify the information in one of the provided example modelsim configuration files to match the paths on your system. Users of a 32-bit flavor of ModelSim should start with simplis_verilog.cfg.modelsim, while a 64-bit flavor will require starting with simplis_verilog.cfg.modelsim64bit. Either edit simplis_verilog.cfg or copy the modified version over top of the existing one in the bin directory as described above. Again, adjust the path to the ModelSim installation directory accordingly.