The S/R Flip-Flop with Set/Reset models a generic clocked S/R Flip-Flop with either asynchronous or synchronous set and reset inputs. The Q and QN outputs can change state only on the specified clock edge unless the asynchronous set or reset is asserted. The clock edge trigger can be set with the Trigger Condition parameter to be either rising edge ( 0_TO_1 ) or falling edge ( 1_TO_0 ). If set and reset inputs are not required, the S/R Flip-Flop can be used.
In this topic:
Model Name: | S/R Flip-Flop with Set/Reset | |||||||||||||||||
Simulator: | ![]() |
This device is compatible with the SIMPLIS simulator. | ||||||||||||||||
Parts Selector Menu Location: | ||||||||||||||||||
Symbol Library: | None - the symbol is automatically generated when placed or edited. | |||||||||||||||||
Model Library: | SIMPLIS_DIGI1.LB | |||||||||||||||||
Subcircuit Names: |
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Symbols: |
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Multiple Selections: | Only one device at a time can be edited. |
To configure the S/R Flip-Flop with Set/Reset, follow these steps:
Label | Parameter Description | ||||||
Clock to Output Delay | Delay from the triggering clock event until the Flip-Flop outputs change | ||||||
Minimum Clk Width | Minimum valid clock width. Clock widths less than this parameter will not trigger the Flip-Flop. | ||||||
Trigger Condition | Determines the
triggering condition of the Flip-Flop clock pin:
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Initial Condition | Initial condition of the Flip-Flop output at time=0 | ||||||
Setup Time | Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | ||||||
Hold Time | Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | ||||||
Ground Ref | Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic. | ||||||
Set/Reset Delay | Delay from when the SET or RST pin goes active until the Q output is actually set or reset. | ||||||
Set/Reset Level | Determines the
Set/Reset level of a device:
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Set/Reset Type | Determines whether or
not output events are synchronized with a clock event:
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To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps:
Label | Parameter Description | |||||||
Input Resistance | Input resistance of each Flip-Flop input pin | |||||||
Hysteresis, Threshold | ![]() |
Hysteresis and
Threshold of the inputs. The hysteretic-window width, HYSTWD
is centered around Threshold (TH) voltage. To
determine the actual threshold ( TL , THI ),
substitute Threshold (TH) and Hysteresis
(HYSTWD) in each of the following formulas:
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Output Resistance | Output resistance of Q and QN pins | |||||||
Output High Voltage | Output high voltage for Q and QN pins | |||||||
Output Low Voltage | Output low voltage for Q and QN pins |
The following truth table assumes a Trigger Condition=0_TO_1 which represents a rising edge clocked Flip-Flop, Set/Reset level=1, and Set/Reset Type=ASYNC, representing asynchronous set/reset.
Asynchronous Set/Reset
Inputs | Outputs | Action | |||||
S | R | CLK | SET | RST | Q | QN | |
1 | 0 |
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0 | 0 | 1 | 0 | Set the Flip-Flop |
0 | 1 |
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0 | 0 | 0 | 1 | Reset the Flip-Flop |
0 or 1 | 0 or 1 | 0 or 1 | 1 | 0 | 1 | 0 | Asynchronously set the Flip-Flop |
0 or 1 | 0 or 1 | 0 or 1 | 0 | 1 | 0 | 1 | Asynchronously reset the Flip-Flop |
0 or 1 | 0 or 1 | 0 or 1 | 1 | 1 | Last Q | Last QN | Illegal concurrent SET and RST |
The following truth table assumes a Trigger Condition=0_TO_1 which represents a rising edge clocked Flip-Flop, Set/Reset level=1, and Set/Reset Type=SYNC, representing synchronous set/reset.
Synchronous Set/Reset
Inputs | Outputs | Action | |||||
S | R | CLK | SET | RST | Q | QN | |
1 | 0 |
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0 | 0 | 1 | 0 | Set the Flip-Flop |
0 | 1 |
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0 | 0 | 0 | 1 | Reset the Flip-Flop |
0 or 1 | 0 or 1 |
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1 | 0 | 1 | 0 | Synchronously set the Flip-Flop |
0 or 1 | 0 or 1 |
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0 | 1 | 0 | 1 | Synchronously reset the Flip-Flop |
0 or 1 | 0 or 1 |
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1 | 1 | Last Q | Last QN | Illegal concurrent SET and RST |
The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_015_srflipflopwsetrst_example.sxsch.
The following waveforms assume Trigger Condition=0_TO_1 which represents a rising edge clocked Flip-Flop, Set/Reset level=1, and Set/Reset Type=ASYNC, representing asynchronous set/reset.
X$U1 3 5 2 4 6 7 SIMPLIS_DIGI1_DFF_SR_N vars: IC=0 MIN_CLK=10p TRIG_COND='0_TO_1' CLK_TO_OUT_DELAY=20p SETUP_TIME=10p HOLD_TIME=1p SET_RESET_DELAY=15p SET_RESET_TYPE='ASYNC' SET_RESET_LEVEL=1 GNDREF='N'
Parameter Name | Label | Data Type | Range | Units | Parameter Description | |||||||
CLK_TO_OUT_DELAY | Clock to Output Delay | Number | 1f to 1024 | s | Delay from the triggering clock event until the Flip-Flop outputs change | |||||||
GNDREF | Ground Ref | String |
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none | Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic. | |||||||
HOLD_TIME | Hold Time | Number | 1f to 1024 | s | Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | |||||||
HYSTWD, TH |
Hysteresis, Threshold |
Number | min: 1f | V | ![]() |
Hysteresis and Threshold of
the inputs. The hysteretic-window width, HYSTWD is centered
around Threshold (TH) voltage. To determine the actual
threshold ( TL , THI ), substitute Threshold
(TH) and Hysteresis (HYSTWD) in each of the
following formulas:
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IC | Initial Condition | Number |
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none | Initial condition of the Flip-Flop output at time=0 | |||||||
MIN_CLK | Minimum Clk Width | Number | 1f to 1024 | s | Minimum valid clock width. Clock widths less than this parameter will not trigger the Flip-Flop. | |||||||
RIN | Input Resistance | Number | min: 100 | Ω | Input resistance of each Flip-Flop input pin | |||||||
ROUT | Output Resistance | Number | min: 1m | Ω | Output resistance of Q and QN pins | |||||||
SETUP_TIME | Setup Time | Number | 1f to 1024 | s | Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | |||||||
SET_RESET_DELAY | Set/Reset Delay | Number | 1f to 1024 | s | Delay from when the SET or RST pin goes active until the Q output is actually set or reset. | |||||||
SET_RESET_LEVEL | Set/Reset Level | Number |
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none | Determines the Set/Reset
level of a device:
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SET_RESET_TYPE | Set/Reset Type | String |
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none | Determines whether or not
output events are synchronized with a clock event:
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TRIG_COND | Trigger Condition | String |
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none | Determines the triggering
condition of the Flip-Flop clock pin:
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VOH | Output High Voltage | Number | any | V | Output high voltage for Q and QN pins | |||||||
VOL | Output Low Voltage | Number | any | V | Output low voltage for Q and QN pins |