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» DVM Test Report: VOUT=1.505V|Bode Plot|Vin Nominal|50% Load
| Test Details | |
| Schematic | 6.3_LTC3406B - DVM ADVANCED.sxsch |
| Test | VOUT=1.505V|Bode Plot|Vin Nominal|50% Load |
| Date / Time | 12/10/2015 5:56 PM |
| Report Directory | promote_graphs\VOUT=1.505V\BodePlot\Vin Nominal\50% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 78.7659% |
| Frequency(CLK) | 955.651k |
| gain_crossover_freq | 20.8851k |
| gain_crossover_freq_nom | 20.8851k |
| gain_margin | 30.3822 |
| gain_margin_nom | 30.3822 |
| ILOAD | AVG 750.312m MIN 748.387m MAX 751.945m RMS 750.313m PK2PK 3.55794m |
| ISRC | AVG 286.895m MIN 423.445u MAX 1.09563 RMS 482.345m PK2PK 1.09521 |
| min_phase | 37.0236 |
| min_phase_freq | 20.8851k |
| phase_crossover_freq | 398.963k |
| phase_margin | 36.9686 |
| phase_margin_nom | 36.9686 |
| Power(LOAD) | 1.12969 |
| Power(SRC) | 1.43424 |
| VLOAD | AVG 1.50562 MIN 1.50176 MAX 1.5089 RMS 1.50563 PK2PK 7.13956m |
| VSRC | AVG 4.99971 MIN 4.9989 MAX 5 RMS 4.99971 PK2PK 1.09521m |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (1.5089) is less than or equal to Max. Output1 Voltage Spec (1.58025) |
| Min_VLOAD | PASS: Min. Output1 Voltage (1.50176) is greater than or equal to Min. Output1 Voltage Spec (1.42975) |
| min_gain_margin | PASS: Gain Margin (30.3822) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (36.9686) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac2_78.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop2_61.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop2_51.sxgph |
 default
CLK
ILOUT
SW
VOUT
|
|
| SXGPH File | simplis_pop2_56.sxgph |
| Other SXGPH Files | |
| clock#pop | simplis_pop2_43.sxgph |
