Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Nominal|90% Load |
Date / Time | 12/10/2015 6:09 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\90% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.3353% |
eta_nom | 95.3353% |
Frequency(CLK) | 85.7447k |
gain_crossover_freq | 4.861k |
gain_margin | 17.4492 |
gmargin_nom | 17.4492 |
gxover_nom | 4.861k |
ILOAD | AVG 4.51692 MIN 4.50847 MAX 4.52198 RMS 4.51692 PK2PK 13.5038m |
iload_nom | 4.51692 |
ISRC | AVG 300.409m MIN -536.321m MAX 1.08473 RMS 544.323m PK2PK 1.62105 |
min_phase | 42.1321 |
min_phase_freq | 4.861k |
phase_crossover_freq | 16.1675k |
phase_margin | 41.7743 |
pmargin_nom | 41.7743 |
Power(LOAD) | 108.802 |
Power(SRC) | 114.126 |
sw_freq_nom | 85.7447k |
VLOAD | AVG 24.0877 MIN 24.0428 MAX 24.1146 RMS 24.0877 PK2PK 71.7912m |
VSRC | AVG 379.97 MIN 379.892 MAX 380.054 RMS 379.97 PK2PK 162.105m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1146) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0428) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (17.4492) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (41.7743) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac13_774.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop13_740.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop13_730.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop13_721.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop13_735.sxgph |
Other SXGPH Files | |
default#763#pop | simplis_pop13_763.sxgph |
Modulator#pop | simplis_pop13_768.sxgph |