Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Nominal|80% Load |
Date / Time | 12/10/2015 6:09 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\80% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.4629% |
eta_nom | 95.4629% |
Frequency(CLK) | 85.9756k |
gain_crossover_freq | 4.8918k |
gain_margin | 18.7152 |
gmargin_nom | 18.7152 |
gxover_nom | 4.8918k |
ILOAD | AVG 4.01579 MIN 4.00911 MAX 4.01983 RMS 4.01579 PK2PK 10.7109m |
iload_nom | 4.01579 |
ISRC | AVG 266.766m MIN -536.048m MAX 994.216m RMS 499.056m PK2PK 1.53026 |
min_phase | 41.8679 |
min_phase_freq | 4.8918k |
phase_crossover_freq | 17.6787k |
phase_margin | 41.5114 |
pmargin_nom | 41.5114 |
Power(LOAD) | 96.7481 |
Power(SRC) | 101.346 |
sw_freq_nom | 85.9756k |
VLOAD | AVG 24.0919 MIN 24.052 MAX 24.116 RMS 24.0919 PK2PK 64.0258m |
VSRC | AVG 379.973 MIN 379.901 MAX 380.054 RMS 379.973 PK2PK 153.026m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.116) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.052) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (18.7152) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (41.5114) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac12_714.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop12_680.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop12_670.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop12_661.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop12_675.sxgph |
Other SXGPH Files | |
Modulator#pop | simplis_pop12_708.sxgph |
default#703#pop | simplis_pop12_703.sxgph |