Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Nominal|5% Load |
Date / Time | 12/10/2015 6:06 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\5% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 94.0099% |
eta_nom | 94.0099% |
Frequency(CLK) | 90.4668k |
gain_crossover_freq | 445.573 |
gain_margin | 30.9799 |
gmargin_nom | 30.9799 |
gxover_nom | 445.573 |
ILOAD | AVG 251.495m MIN 251.467m MAX 251.539m RMS 251.495m PK2PK 71.9745u |
iload_nom | 251.495m |
ISRC | AVG 16.9771m MIN -511.272m MAX 519.975m RMS 220.696m PK2PK 1.03125 |
min_phase | 97.3623 |
min_phase_freq | 91.7776 |
phase_crossover_freq | 44.134k |
phase_margin | 113.117 |
pmargin_nom | 113.117 |
Power(LOAD) | 6.06027 |
Power(SRC) | 6.44642 |
sw_freq_nom | 90.4668k |
VLOAD | AVG 24.097 MIN 24.0944 MAX 24.1009 RMS 24.097 PK2PK 6.46275m |
VSRC | AVG 379.998 MIN 379.948 MAX 380.051 RMS 379.998 PK2PK 103.125m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1009) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0944) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (30.9799) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (113.117) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac1_54.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop1_20.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop1_10.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop1_1.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop1_15.sxgph |
Other SXGPH Files | |
default#43#pop | simplis_pop1_43.sxgph |
Modulator#pop | simplis_pop1_48.sxgph |