Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Nominal|30% Load |
Date / Time | 12/10/2015 6:08 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\30% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.9105% |
eta_nom | 95.9105% |
Frequency(CLK) | 87.5065k |
gain_crossover_freq | 4.76088k |
gain_margin | 27.1025 |
gmargin_nom | 27.1025 |
gxover_nom | 4.76088k |
ILOAD | AVG 1.50653 MIN 1.50559 MAX 1.50726 RMS 1.50653 PK2PK 1.67311m |
iload_nom | 1.50653 |
ISRC | AVG 99.6318m MIN -539.989m MAX 614.535m RMS 306.305m PK2PK 1.15452 |
min_phase | 49.0124 |
min_phase_freq | 4.76088k |
phase_crossover_freq | 33.0239k |
phase_margin | 48.8263 |
pmargin_nom | 48.8263 |
Power(LOAD) | 36.3028 |
Power(SRC) | 37.8507 |
sw_freq_nom | 87.5065k |
VLOAD | AVG 24.0969 MIN 24.082 MAX 24.1085 RMS 24.0969 PK2PK 26.4664m |
VSRC | AVG 379.99 MIN 379.939 MAX 380.054 RMS 379.99 PK2PK 115.452m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1085) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.082) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (27.1025) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (48.8263) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac6_354.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop6_320.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop6_310.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop6_301.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop6_315.sxgph |
Other SXGPH Files | |
default#343#pop | simplis_pop6_343.sxgph |
Modulator#pop | simplis_pop6_348.sxgph |