Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Minimum|20% Load |
Date / Time | 12/10/2015 6:14 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\20% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.6358% |
eta_min | 95.6358% |
Frequency(CLK) | 80.174k |
gain_crossover_freq | 4.73763k |
gain_margin | 26.2307 |
gmargin_min | 26.2307 |
gxover_min | 4.73763k |
ILOAD | AVG 1.00448 MIN 1.00406 MAX 1.00493 RMS 1.00448 PK2PK 877.94u |
iload_min | 1.00448 |
ISRC | AVG 70.3276m MIN -577.901m MAX 583.619m RMS 292.908m PK2PK 1.16152 |
min_phase | 49.896 |
min_phase_freq | 4.73763k |
phase_crossover_freq | 31.6165k |
phase_margin | 49.7419 |
pmargin_min | 49.7419 |
Power(LOAD) | 24.2048 |
Power(SRC) | 25.3094 |
sw_freq_min | 80.174k |
VLOAD | AVG 24.0968 MIN 24.0868 MAX 24.1075 RMS 24.0968 PK2PK 20.713m |
VSRC | AVG 359.993 MIN 359.942 MAX 360.058 RMS 359.993 PK2PK 116.152m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1075) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0868) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (26.2307) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (49.7419) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac32_1914.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop32_1880.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop32_1870.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop32_1861.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop32_1875.sxgph |
Other SXGPH Files | |
default#1903#pop | simplis_pop32_1903.sxgph |
Modulator#pop | simplis_pop32_1908.sxgph |