Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Minimum|10% Load |
Date / Time | 12/10/2015 6:14 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\10% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 94.9649% |
eta_min | 94.9649% |
Frequency(CLK) | 80.8563k |
gain_crossover_freq | 2.9502k |
gain_margin | 27.3278 |
gmargin_min | 27.3278 |
gxover_min | 2.9502k |
ILOAD | AVG 502.466m MIN 502.357m MAX 502.616m RMS 502.466m PK2PK 259.039u |
iload_min | 502.466m |
ISRC | AVG 35.4349m MIN -567.826m MAX 580.845m RMS 259.909m PK2PK 1.14867 |
min_phase | 92.821 |
min_phase_freq | 2.9502k |
phase_crossover_freq | 34.3931k |
phase_margin | 92.7916 |
pmargin_min | 92.7916 |
Power(LOAD) | 12.1079 |
Power(SRC) | 12.7498 |
sw_freq_min | 80.8563k |
VLOAD | AVG 24.0969 MIN 24.0918 MAX 24.1038 RMS 24.0969 PK2PK 12.0189m |
VSRC | AVG 359.996 MIN 359.942 MAX 360.057 RMS 359.996 PK2PK 114.867m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1038) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0918) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (27.3278) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (92.7916) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac30_1794.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop30_1760.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop30_1750.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop30_1741.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
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SXGPH File | simplis_pop30_1755.sxgph |
Other SXGPH Files | |
default#1783#pop | simplis_pop30_1783.sxgph |
Modulator#pop | simplis_pop30_1788.sxgph |