Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|80% Load |
Date / Time | 12/10/2015 6:13 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\80% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.4930% |
eta_max | 95.4930% |
Frequency(CLK) | 93.6214k |
gain_crossover_freq | 5.44648k |
gain_margin | 21.1075 |
gmargin_max | 21.1075 |
gxover_max | 5.44648k |
ILOAD | AVG 4.016 MIN 4.00935 MAX 4.01953 RMS 4.01601 PK2PK 10.1822m |
iload_max | 4.016 |
ISRC | AVG 253.373m MIN -697.228m MAX 981.234m RMS 495.566m PK2PK 1.67846 |
min_phase | 57.2504 |
min_phase_freq | 5.44648k |
phase_crossover_freq | 23.8124k |
phase_margin | 57.1885 |
pmargin_max | 57.1885 |
Power(LOAD) | 96.7578 |
Power(SRC) | 101.325 |
sw_freq_max | 93.6214k |
VLOAD | AVG 24.093 MIN 24.0532 MAX 24.1141 RMS 24.0931 PK2PK 60.8857m |
VSRC | AVG 399.975 MIN 399.902 MAX 400.07 RMS 399.975 PK2PK 167.846m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1141) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0532) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (21.1075) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (57.1885) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac26_1554.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop26_1520.sxgph |
SRC
ISRC
VSRC
|
|
SXGPH File | simplis_pop26_1510.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop26_1501.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
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SXGPH File | simplis_pop26_1515.sxgph |
Other SXGPH Files | |
default#1543#pop | simplis_pop26_1543.sxgph |
Modulator#pop | simplis_pop26_1548.sxgph |