Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|60% Load |
Date / Time | 12/10/2015 6:12 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\60% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.7362% |
eta_max | 95.7362% |
Frequency(CLK) | 94.7282k |
gain_crossover_freq | 4.83157k |
gain_margin | 24.2796 |
gmargin_max | 24.2796 |
gxover_max | 4.83157k |
ILOAD | AVG 3.01236 MIN 3.00861 MAX 3.01442 RMS 3.01236 PK2PK 5.80561m |
iload_max | 3.01236 |
ISRC | AVG 189.579m MIN -632.395m MAX 815.909m RMS 407.292m PK2PK 1.4483 |
min_phase | 67.0477 |
min_phase_freq | 4.83157k |
phase_crossover_freq | 28.4384k |
phase_margin | 66.8014 |
pmargin_max | 66.8014 |
Power(LOAD) | 72.5823 |
Power(SRC) | 75.8149 |
sw_freq_max | 94.7282k |
VLOAD | AVG 24.0948 MIN 24.065 MAX 24.1112 RMS 24.0949 PK2PK 46.233m |
VSRC | AVG 399.981 MIN 399.918 MAX 400.063 RMS 399.981 PK2PK 144.83m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1112) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.065) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (24.2796) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (66.8014) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac24_1434.sxgph |
LOAD
ILOAD
VLOAD
|
|
SXGPH File | simplis_pop24_1400.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop24_1390.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop24_1381.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
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SXGPH File | simplis_pop24_1395.sxgph |
Other SXGPH Files | |
default#1423#pop | simplis_pop24_1423.sxgph |
Modulator#pop | simplis_pop24_1428.sxgph |