Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|5% Load |
Date / Time | 12/10/2015 6:10 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\5% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 94.5606% |
eta_max | 94.5606% |
Frequency(CLK) | 102.537k |
gain_crossover_freq | 247.419 |
gain_margin | 33.9831 |
gmargin_max | 33.9831 |
gxover_max | 247.419 |
ILOAD | AVG 251.543m MIN 251.515m MAX 251.58m RMS 251.543m PK2PK 65.2387u |
iload_max | 251.543m |
ISRC | AVG 16.0352m MIN -459.56m MAX 473.724m RMS 198.064m PK2PK 933.284m |
min_phase | 96.9774 |
min_phase_freq | 91.3835 |
phase_crossover_freq | 52.0421k |
phase_margin | 106.052 |
pmargin_max | 106.052 |
Power(LOAD) | 6.06146 |
Power(SRC) | 6.41014 |
sw_freq_max | 102.537k |
VLOAD | AVG 24.0971 MIN 24.0946 MAX 24.1004 RMS 24.0971 PK2PK 5.85768m |
VSRC | AVG 399.998 MIN 399.953 MAX 400.046 RMS 399.998 PK2PK 93.3284m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1004) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0946) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (33.9831) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (106.052) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac15_894.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop15_860.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop15_850.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop15_841.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop15_855.sxgph |
Other SXGPH Files | |
default#883#pop | simplis_pop15_883.sxgph |
Modulator#pop | simplis_pop15_888.sxgph |