Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|10% Load |
Date / Time | 12/10/2015 6:10 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\10% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.5348% |
eta_max | 95.5348% |
Frequency(CLK) | 100.251k |
gain_crossover_freq | 683.346 |
gain_margin | 32.5624 |
gmargin_max | 32.5624 |
gxover_max | 683.346 |
ILOAD | AVG 502.545m MIN 502.437m MAX 502.656m RMS 502.545m PK2PK 218.53u |
iload_max | 502.545m |
ISRC | AVG 31.7018m MIN -474.448m MAX 513.604m RMS 219.881m PK2PK 988.052m |
min_phase | 109.748 |
min_phase_freq | 135.936 |
phase_crossover_freq | 46.8562k |
phase_margin | 118.002 |
pmargin_max | 118.002 |
Power(LOAD) | 12.1099 |
Power(SRC) | 12.6759 |
sw_freq_max | 100.251k |
VLOAD | AVG 24.0971 MIN 24.0921 MAX 24.1022 RMS 24.0971 PK2PK 10.1382m |
VSRC | AVG 399.997 MIN 399.949 MAX 400.047 RMS 399.997 PK2PK 98.8052m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1022) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0921) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (32.5624) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (118.002) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac16_954.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop16_920.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop16_910.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop16_901.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop16_915.sxgph |
Other SXGPH Files | |
default#943#pop | simplis_pop16_943.sxgph |
Modulator#pop | simplis_pop16_948.sxgph |